A Decoder – Look up Tables for FPGAs

Timing Defect Analysis in Look-Up Tables of SRAM-Based FPGAs

The objective of our article is to demonstrate that some physical defects in a LUT can change its propagation delay. We propose a simplified 'timing' model of the LUT which determines its propagation delay. Such a model is exploited to analyse the effects of a defect on the LUT behaviour, from which we demonstrate that they can cause a timing fault on it. Anywhere in a LUT, a timing defect can ...

A Quick Tables Look-up Optimization Algorithm for CAVLC Decoding

In this paper, a quick table look-up optimization algorithm is presented to solve the problems of long table look-up time for CAVLC decoding in H.264/AVC. The achievement of the new algorithm rests that we make full use of the hash table query and index technology to improve the table look-up speed for CAVLC decoding. The basic idea of the new algorithm is that we take the number of zero in cod...

A High Efficient Tables Look-up Algorithm for CAVLC Decoding

In order to solve the problems of high table memory access and long table look-up time and big table storage space in the process of CAVLC decoding for H.264/AVC, a high efficient table look-up algorithm is presented in this paper. The contribution of this paper lies that we uses a program method to realize fully the no-table looking-up of codeword. Specifically, after finding the relationships...

Digital Look Up Tables and Real Number

Rijndael FPGA Implementations Utilising Look-Up Tables

This paper presents single-chip FPGA Rijndael algorithm implementations of the Advanced Encryption Standard (AES) algorithm, Rijndael. In particular, the designs utilise look-up tables to implement the entire Rijndael Round function. A comparison is provided between these designs and similar existing implementations. Hardware implementations of encryption algorithms prove much faster than equiv...